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Method for making a silicon-on-insulator MOS transistor using a selective SiGe epitaxy
Author
admgenie
Date
2024-03-25
Views
371
Disclosed is a method for manufacturing a metal-oxide-semiconductor (MOS) device formed in an epitaxial silicon layer on insulator substrate comprising the steps of forming a field oxide layer defined an active region of the MOS device in the silicon layer and forming a gate oxide on the silicon layer; forming a gate electrode on the gate oxide, and self-aligned implanting a dopant of low concentration to form a lightly doped drain region; forming an oxide spacer in both sides of the gate electrode; growing a SiGe epitaxial layer having a lower bandgap than the silicon layer on the portion of the exposed silicon layer; and implanting a dopant of high concentration over the SiGe epitaxial layer to form a highly doped source/drain region. This invention can easily manufacture an SOI MOS device having a low source/drain series resistance and a high breakdown voltage without additional complex processes.
등록번호/일자 06048756 (2000.04.11)
등록번호/일자 06048756 (2000.04.11)