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서울대학교 이종호 교수님 연구실Semiconductor Materials and Devices Laboratory

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Home 3-D Stacked Synapse Array Based on Charge-Trap Flash Memory for Implementation of Deep Neural Networks

Home 3-D Stacked Synapse Array Based on Charge-Trap Flash Memory for Implementation of Deep Neural Networks

3-D Stacked Synapse Array Based on Charge-Trap Flash Memory for Implementation of Deep Neural Networks

저자

Yu Jeong Park et al.

저널 정보

IEEE Transactions on Electron Devices

출간연도

2019

링크

https://doi.org/10.1109/TED.2018.2881972

3-D Stacked Synapse Array Based on Charge-Trap Flash Memory for Implementation of Deep Neural Networks