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서울대학교 이종호 교수님 연구실Semiconductor Materials and Devices Laboratory

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Home Design Consideration of Self-Aligned Recessed Channel (RC) Devices in Sub-100 nm CMOS Technology

Home Design Consideration of Self-Aligned Recessed Channel (RC) Devices in Sub-100 nm CMOS Technology

Design Consideration of Self-Aligned Recessed Channel (RC) Devices in Sub-100 nm CMOS Technology

저자

Doo-Yeon Chung et al.

저널 정보

Journal of the Korean Physical Society

출간연도

2000

링크

https://doi.org/10.3938/jkps.37.617

Design Consideration of Self-Aligned Recessed Channel (RC) Devices in Sub-100 nm CMOS Technology