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서울대학교 이종호 교수님 연구실Semiconductor Materials and Devices Laboratory

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Home Fabrication of asymmetric independent dual-gate FinFET using sidewall spacer patterning and CMP processes

Home Fabrication of asymmetric independent dual-gate FinFET using sidewall spacer patterning and CMP processes

Fabrication of asymmetric independent dual-gate FinFET using sidewall spacer patterning and CMP processes

저자

Hyungjin Kim et al.

저널 정보

Microelectronic Engineering

출간연도

2018

링크

https://doi.org/10.1016/j.mee.2017.10.014

Fabrication of asymmetric independent dual-gate FinFET using sidewall spacer patterning and CMP processes