Home Gate Workfunction Engineering in Bulk FinFETs for Sub-50-nm DRAM Cell Transistors
저자
Ki-Heung Park et al.
저널 정보
IEEE Electron Device Letters
출간연도
2007
링크
https://doi.org/10.1109/LED.2006.889235
Gate Workfunction Engineering in Bulk FinFETs for Sub-50-nm DRAM Cell Transistors
