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서울대학교 이종호 교수님 연구실Semiconductor Materials and Devices Laboratory

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Home Modeling of ΔIBL due to random telegraph noise with considering bit-line interference in NAND flash

Home Modeling of ΔIBL due to random telegraph noise with considering bit-line interference in NAND flash

Modeling of ΔIBL due to random telegraph noise with considering bit-line interference in NAND flash

저자

Sung-Min Joe et al.

저널 정보

Semiconductor Science and Technology

출간연도

2014

링크

https://doi.org/10.1088/0268-1242/29/12/125013

Modeling of ΔIBL due to random telegraph noise with considering bit-line interference in NAND flash