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서울대학교 이종호 교수님 연구실Semiconductor Materials and Devices Laboratory

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Home Design Consideration of Bulk FinFETs Devices With n+/p+/n+ Gate and p+/n+ Gate for Sub-50-nm DRAM Cell Transistors

Home Design Consideration of Bulk FinFETs Devices With n+/p+/n+ Gate and p+/n+ Gate for Sub-50-nm DRAM Cell Transistors

Design Consideration of Bulk FinFETs Devices With n+/p+/n+ Gate and p+/n+ Gate for Sub-50-nm DRAM Cell Transistors

저자

Ki-Heung Park et al.

저널 정보

IEEE TRANSACTIONS ON NANOTECHNOLOGY

출간연도

2008

링크

https://doi.org/10.1109/TNANO.2008.926381

Design Consideration of Bulk FinFETs Devices With n+/p+/n+ Gate and p+/n+ Gate for Sub-50-nm DRAM Cell Transistors