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서울대학교 이종호 교수님 연구실Semiconductor Materials and Devices Laboratory

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Home Simulation of the effect of parasitic channel height on characteristics of stacked gate-all-around nanosheet FET

Home Simulation of the effect of parasitic channel height on characteristics of stacked gate-all-around nanosheet FET

Simulation of the effect of parasitic channel height on characteristics of stacked gate-all-around nanosheet FET

저자

Yunho Choi et al.

저널 정보

Solid-State Electronics

출간연도

2020

링크

https://doi.org/10.1016/j.sse.2019.107686

Simulation of the effect of parasitic channel height on characteristics of stacked gate-all-around nanosheet FET