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서울대학교 이종호 교수님 연구실Semiconductor Materials and Devices Laboratory

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Home Simulation Study of High-Performance Modified Saddle MOSFET for Sub-50-nm DRAM Cell Transistors

Home Simulation Study of High-Performance Modified Saddle MOSFET for Sub-50-nm DRAM Cell Transistors

Simulation Study of High-Performance Modified Saddle MOSFET for Sub-50-nm DRAM Cell Transistors

저자

Ki-Heung Park et al.

저널 정보

IEEE ELECTRON DEVICE LETTERS

출간연도

2006

링크

https://doi.org/10.1109/LED.2006.880833

Simulation Study of High-Performance Modified Saddle MOSFET for Sub-50-nm DRAM Cell Transistors